1. Field of the Invention
The present invention relates to the manufacturing of semiconductor memory devices, such as non-volatile memories of the flash EEPROM (Electrically Erasable Programmable Read-Only Memories) type. Flash EEPROM memories can be erased with one operation in all the cells forming the memory.
2. Description of the Related Art
As it is well known in this particular technical field, re-programmable non-volatile memory cells, in particular flash EEPROM cells, are structured as a floating gate FETs (Field-Effect Transistors) and have a dielectric layer, called the interpoly dielectric, provided between their floating and control gate regions, this dielectric layer functioning as an insulator to the charge stored in the floating gate. The absence or presence of charge in the floating gate effectively sets the logic state of the memory, which logic state is defined as 0 or 1 in the binary code.
The above dielectric layer is obtained in different ways and made out of different materials. A common procedure is to deposit three dielectric layers successively onto the floating gate region, this region being formed by a layer of amorphous or polycrystalline silicon (polysilicon) deposited onto a thin layer of silicon oxide known as the tunnel oxide. The so obtained multiple dielectric layer comprises: a first layer of silicon oxide, a second layer of silicon nitride, and a third layer of silicon oxide. The resulting dielectric is known as the ONO or ONO interpoly dielectric, as it is shown in FIG. 1.
Within the ONO layer, the cell capability to retain its logic state is mainly guaranteed by the two layers of silicon oxide. Indeed, the nitride layer facilitates integration of the triple layer inside the flow of the device manufacturing process. During the manufacturing steps that follow the formation of the interpoly dielectric, treatments made with oxidizing species (O2, O, OH, H2O) are applied. The nitride acts as a barrier against the diffusion of the oxidizing species to the floating gate, since it is not permeable to said oxidizing species. Thus, its presence is effective to prevent further oxidation of the floating gate, and therefore, the thickness of the interpoly dielectric from being changed in the course of subsequent steps of the device manufacturing process. In the state of the art, the need to have a nitride layer maintained sufficiently thick to shield from subsequent thermal treatments, and the concurrent need to keep the retention capability of the ONO layer unchanged, disallows to reduce the overall electrical thickness of the triple layer below 140 Angstroms.
Instead of ONO layer, a single oxide interpoly layer may be used whenever, in specific memory cells, the interpoly dielectric is not required to be particularly thin and/or no oxidizing treatments are provided after its formation. The thickness of the interpoly dielectric is, irrespective of its composition and forming method, jointly responsible of the capacitive coupling of the memory cell. Accordingly, it enters the setting of program and erase parameters, additionally to ensuring retention of the logic state over time.
A pressing demand for increased miniaturization of electronic devices and reduced power absorption, and the consequent need for ever lower device bias voltages, is urging recourse to active dielectrics of reduced thickness at no trade-off of their performance characteristics.
It has been proposed, in prior patent specifications to the filing date of this Application, that a layer of silicon nitride be included in the manufacturing of flash memory cells. This layer is used in the ONO triple layer, and used for protection against mechanical and thermal stressing during the intermediate manufacturing steps, but is removed before the manufacturing process is completed. Such are the teachings of U.S. Pat. No. 5,352,619, for instance, which is incorporated herein by reference in its entirety.
U.S. Pat. No. 6,137,132, which is incorporated herein by reference in its entirety, discloses using the silicon nitride as an anti-reflection material for the subsequent photoetching application. According to U.S. Pat. No. 5,926,730, which is incorporated herein by reference in its entirety, the silicon nitride is provided at the interface between the bottom silicon layer and a conductive layer within an active dielectric stack.